1) Field of the Invention
This invention relates generally to the structure and fabrication of alignment marks on semiconductor chips and particularly to the fabrication of alignment marks in a semiconductor process using trench isolation (STI) and chemical mechanical polishing (CMP). The invention provides a process for removing oxide, which is used to fill isolation trenches, from over alignment marks and from over active areas.
2) Description of the Prior Art
The fabrication of microcircuit devices on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic masks on the wafer. The masking step includes an etching step and defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition and impurity introduction.
In the production of integrate circuit structures, it has become increasingly important to provide structures having a plurality of metallization layers due the ever increasing density of the circuit elements in the structure. Further, as the device and feature sizes becoming smaller, it is important that the photolithographic mask be aligned precisely with the wafer during the masking step to minimize the misalignment between the layers. Most alignment schemes require the use of alignment targets that were defined on the wafers in the previous layer. One such scheme involves the use of two alignment targets that were defined on the wafer subsequent layers being aligned with respect to these two alignment targets. Typically, each alignment target comprises topographical marks which can be formed by etching into the wafer a plurality of steps with a height of, for example 1200.ANG.. The alignment targets are used to diffract a laser alignment beam generated by a photolithography machine, commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative position of the wafer and the photolithographic mask is adjusted accordingly so that the pattern for the photolithographic mask are transferred to the wafer in the precise location as desired.
However, to meet the demand for more metal and insulating layers in devices and the stringent depth of focus requirement for submicron lithography, a new planarization technique, commonly known as chemical-mechanical polishing (CMP) is used. Typically, CMP planarization of the wafer involves holding the wafer against a rotating polishing pad wet with a silica-based alkaline slurry and at the same time applying pressure. Unlike the conventional planarization techniques, the CMP planarization technique provides a global planarization, that is, one that provides a large planarization range the generally covers the whole wafer surface. Since the planarization range is large, the steps of the alignment targets on a new overlying layer on the wafer will be flattened after it is planarized by a the CMP technique. The steps of the alignment targets on the previous layer are not replicated to the overlying layer. The overlying layer will cause alignment target reading problems by interfering with the diffraction pattern, especially where the overlying layer is a thick oxide or a nitride layer. The problem is even worse with when the newly formed overlying layer is highly reflective or opaque.
New isolation processes, such as shallow trench isolation (STI) create a thick oxide layer over the alignment marks and create the readability problems described above. In the STI process, a silicon nitride layer is formed on a wafer and patterned to have openings where trenches will be formed. Trenches are etched in the substrate. A thick oxide layer is deposited in the trenches and over wafer surface. Next, the thick oxide layer is polished (CMP) to create a planar surface.
As shown in FIG. 1, the inventor has found that the inventor's CMP process leaves a thick oxide layer 38B over the alignment marks 30 that interferes with a alignment mark reader, such as on an ASM stepper. FIG. 1 is a cross sectional view taken after a CMP process. The Conventional alignment marks (e.g., grooves or channels) 30 in an alignment mark (AM) area 18 have the thick insulating layer 38B (over the nitride layer 22 and pad oxide layer 20). A pad oxide layer 20 and a barrier layer 32 are formed over the substrate 10. As can be seen, after the CMP, the insulating layer 38B covers the alignment marks 30 and does not replicate the alignment mark topography. The oxide 38B over the alignment mark area 18 is thicker than the oxide layer 38A over the device areas 14 because the open areas 13 between the device area and the alignment marks do not have any pattern (smooth topology with no trenches). The inventor has found that the oxide 38B can be between 2000 and 4000 .ANG. thicker than the oxide 39A over the device area even after chemical-mechanical polishing.
A non-optimum alternative is to over polish the wafer, thus removing most of the thick oxide over the alignment marks, but at the same time the over polishing removes oxide from the trenches, thus creating isolation and yield problems.
Other practitioners have proposed solutions to the non-readable alignment mark problem. U.S. Pat. No. 5,627,100 (Lee) shows a method for eliminating the window mask process when using a CMP process. U.S. Pat. No. 5,128,283 (Tanaka) shows a method of forming mask alignment marks. U.S. Pat. No. 5,356,513 (Burke) shows a method of forming a polished stop planarization using chemical-mechanical polishing (CMP). However, these methods can be improved over to provide a simpler process and further improve the readability of the alignment marks.